In early data processing systems, the processor periodically polled each of the various resources, such as tape drives, card readers and printers, in order to ascertain whether the resource required servicing by the processor. In these systems, the relative priority of the resources depended upon the ordering of the resources in the software polling loop executed by the processor. However, significant processing time was wasted in polling resources which were inactive or otherwise not in need of servicing.
With advances in the design of the processor to allow the instruction processing sequence to be interrupted, resources were allowed to request servicing by the processor when necessary. However, most such systems implemented a single interrupt path, and the processor had to determine which resource generated the interrupt as the first step in the interrupt servicing routine. Later processors provided more than one interrupt path, but even in such processors more resources could be present than there were interrupt paths, and the processor still had to determine which resource was requesting service. Even in those large data processing systems wherein many interrupt levels were provided, the extensive interrupt priority networks necessary to resolve conflicts tended to be quite complex and expensive.
In more recent data processing systems, the flexibility of the interrupt mechanism has been enhanced by allowing the user to dynamically alter the relative priorities of the several interrupt levels. In those systems wherein the user has complete flexibility in defining the priority ordering, the required circuitry expands more than exponentially for each additional level of priority. Typical of such systems are those shown in U.S. Pat. Nos. 3,925,766/4,001,784 and 4,035,780. In most systems, however, significant circuitry is saved by offering the user less than full alterability. This latter solution has become typical in single-chip microcomputer systems.
For example, in the Intel 8051 microcomputer, each of five interrupt sources may have either a high of a low priority level depending upon the state of a corresponding user-accessible control bit. Within each level, the relative priority of the several sources is fixed. Although a high-priority level interrupt will interrupt the servicing of a low-priority level interrupt, neither level interrupt will interrupt the servicing of the same or higher level interrupt. Thus, using this compromise, the user can dynamically shift levels but not priority within level. In order to be sure that a particular interrupt will have the highest priority, the user must reduce all of the interrupts to the lowest level.
In contrast, in the Zilog Z8 microcomputer, the six available interrupt levels are arbitrarily grouped into three groups of two each. A respective one of three user-accessible control bits defines the relative priority of the two levels within each group. An additional three user-accessible control bits defines the relative priority between the three groups. Thus, using this rather complicated mechanism, the user can dynamically redefine the six priority levels in 48 of the 720 possible orderings. However, by changing the group priorities, the user necessarily redefines the relative priority of both of the interrupt levels within each group and cannot generally redefine the priority of only one of the interrupt levels.
Each of the known fully alterable interrupt priority mechanisms is less than satisfactory in terms of circuit complexity if the user only needs the ability to selectively define the particular one of the several interrupt sources as having the highest priority. Similarly, the known compromise schemes preclude the user from dynamically selecting the highest priority interrupt source while preserving the ability of each of the priority levels to interrupt the servicing of even lower priority levels.